EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
Nature

Dynamic Scheduling and Decoding Algorithms for LDPC and Reed-Solomon Codes

Dynamic scheduling and decoding algorithms have become pivotal in advancing the performance of error-correcting codes. Recent innovations have focused on refining Low-Density Parity-Check (LDPC) codes ...
EDN

LDPC: Another Key Step Toward Shannon

For communication designers, especially those in the networking and wireless field, the Shannon limit can be seen as the Holy Grail. And, since being first defined in ...
Design-Reuse

IEEE802.11n/ac/ax Wi-Fi LDPC Encoder and Decoder FEC IP Core Available For Licensing and Implementation from Global IP Core

December 6, 2022 - Global IP Core Sales - The new IEEE802.11n/ac/ax Wi-Fi LDPC Encoder and Decoder FEC IP Core is developed for high throughput WLAN applications. The IEEE802.11n/ac/ax Wi-Fi LDPC ...
Design-Reuse

Creonic to Supply New LDPC Decoder and Encoder IP Cores for CCSDS Standard

Kaiserslautern, Germany, Apr. 30 2015 – Creonic GmbH, a leading IP core provider for communications, announced today the release of their new CCSDS LDPC encoder and decoder IP cores for the satellite ...